Process, voltage, temperature, parasitics, and power (PVTPP) variations are often modeled as a set of PVTPP corners. Traditionally, without considering parasitics and power variations, only a handful of corners have been necessary: with FF (fast fast) and SS (slow slow) process corners, plus extreme values for voltage and temperature. The total number of combinations in such a case is 23=8, which is the number of possible corners (PVTPP corners).
With modern processes, many more process corners are often needed to properly bracket process variation across different device types. Furthermore, transistors are smaller, performance margins are smaller, voltages are lower, and there may be multiple supply voltages. To bracket these variations, more variables with more values per variable are needed. This leads to more corners.
As shown above, a circuit with 3 variables having 2 values each gave 23=8 corners. Now, even a basic analysis of an electrical circuit design having four device types (e.g. NMOS, PMOS, resistor, capacitor) and 4 other variables (e.g. temperature, voltage, bias, load) with 3 values each results in 38=6,561 corners.
The problem gets worse with double patterning lithography (DPL), where the RC (resistor capacitor) parasitics among the masks degrade performance. To account for these, a tactic is to treat the RC parasitics as corners, leading to about a fifteen times increase in the number of model sets, and therefore a fifteen times increase in the total number of corners.
Further, power verification needs corners for each power setting (e.g. quick boot, cruising, and standby), which also increases the total number of corners. In general, there is a set of variables (power, voltage, temperature, parasitics, power setting, etc), and each variable has a set of values. The designer is interested in finding the value for each variable (the “corner”) that gives the worst-case performance (minimum or maximum performance) of all possible corners. The common element among these PVTPP variables is that the design performance is judged on each combination of conditions (the whole set of possible PVTPP corners) and it is the worst-case performance among the whole set of possible PVTPP corners that is of greatest concern. In this framework, the PVTPP variables do not follow a probability distribution; the worst-case must be found in the whole space of PVTPP variables. Of note, in the context of the present disclosure, PVTPP variables exclude global process variables modeled using a distribution, and local process variables modeled using a distribution.
The problem facing circuit designers is that simulating each corner can take several seconds, minutes, or even hours for longer analyses. To simulate all possible corners could take hours or even days, which is too time-consuming. Designers may cope by guessing which corners cause the worst-case performance, but that is risky: a wrong guess could mean that the design has not accounted for the true worst-case, which means failure in testing, followed by a re-spin of the design, or worse, failure in the field.
Finding the worst-case PVTPP corners is part a design loop where the designer (circuit designer) will be changing circuit design variables such as Ws (widths) and Ls (lengths), in order to find the design with the best performance under the worst-case PVTPP conditions.
Different approaches (flows) for designing/verifying electrical circuit designs (ECDs) are shown at FIGS. 1-5. The time taken for each flow is measured and compared for an exemplary ECD, which is VCO of a PLL, from the TSMC AMS Reference Flow 2.0, on 28 nm TSMC process. The ECD in question has two output performance measures, namely duty cycle and gain, with specifications (specs) of: 48.3<duty cycle<51.7%, and 3<Gain<4.4 GHz/V. The variables of the ECD are temperature, Vah,vdd, Va,vdd, Vd,vdd, and 15 model sets (FF, TT, SS, etc.). All combinations of all values of variables lead to 3375 corners (full-factorial scenario). Since there are two output performance measures, and each output has a lower and upper bound, there are up to 2×2=4 PVTPP corners that cause worst-case performance. We used a popular commercial simulator to simulate the ECD.
Because the flows of FIGS. 1-5 include changing design variables, we need a way to compare different approaches in a fair fashion, which is independent of designer skill and how much knowledge the designer has about the circuit. We do this with a simple, reasonable approximation: in the design loop, the designer considers 50 designs. Also, since this is the age of multi-core and multi-machine parallel processing, we always consider each approach to have 10 cores running in parallel.
FIG. 1 shows a prior art flow in which a designer simply chooses to simulate all possible PVTPP corners at each iteration of the electrical circuit design (ECD). At action 50, the topology and initial sizing of the ECD are set. At action 52, the ECD goes through multiple iterations of sizing and testing at all possible PVTPP corners. At action 54, the final ECD proceeds to layout and parasitic extraction (RCX). At action 56, the ECD proceeds to fabrication and is tested at action 58. The flow of FIG. 1 is very accurate (to the extent that PVTPP variation is an accurate model of variation). However, since each of 50 design iterations takes 3375 simulations (e.g., Simulation Program with Integrated Circuit Emphasis (SPICE) simulations), then it is very slow, taking 13.5 days even when on 10 parallel cores.
FIG. 2 shows another prior art flow where the designer guesses worst case PVTPP corners. After choosing a topology and initial sizing of the ECD at action 50, the designer uses his expertise and experience with the ECD to guess, at action 60, which PVTPP corners cause worst-case performance, without any simulations. Then, he simply designs against those corners at action 62. The advantage of this approach is its speed, because it requires no simulations to select corners, and each design iteration only has to be simulated on the four selected corners (upper and lower specification for each of two outputs). The disadvantage is accuracy or reliability: if the designer's guess of worst-case PVTPP corner was wrong, then the estimate of worst-case performance is overly optimistic. This can be an important issue. For example, in power verification, it could mean that the circuit may not hit the power budget. This in turn translates, for example, into poor battery life on mobile devices.
FIG. 3 shows another prior art flow, which is similar to that of FIG. 2 but comprises a verification action 64 that runs all combinations of PVTPP corners (full-factorial) after the design step. This ensures that the circuit is verified against the target specs (performance specifications). However, it is possible that the verification step found new worst-case PVTPP corners that make the ECD fail specs, or that made the ECD have worse performances than the performance on the current PVTPP corners. To pass against these new PVTPP corners, the design needs to be improved on these corners, and verified again. This takes more simulations and time.
Overall, the flow of FIG. 3 is more accurate than the flow of FIG. 2, but the full-factorial steps are quite slow, which make the overall runtime quite slow (15.2 hours on our example circuit). Also, the extra design round is non-ideal.
FIG. 4 shows another prior art flow that addresses an issue of the flow of FIG. 3, which needs an extra design round because the initially chosen corners likely did not represent the worst-case.
One of the concepts of the flow of FIG. 4 is to simulate, at action 66, all corner combinations (full-factorial) after the topology and initial sizing of the ECD are set, to “extract” good worst-case PVTPP corners. Then, the user designs against these corners. Subsequently, in case there were strong interactions between design variables and PVTPP variables, the user runs full-factorial PVT. Usually, PVTPP corners that were extracted earlier will remain as the worst-case corners; though if not, the user designs against the new worst-case corners and verifies again.
Overall, the flow of FIG. 4 has a comparable runtime and accuracy to the flow of FIG. 3, but typically only needs one design round (instead of two for the flow of FIG. 3) because PVTPP design is always against good corners. The flow of FIG. 4 is accurate, but still fairly slow because it has to run full-factorial PVTPP twice (14.2 hours on our example circuit).
Therefore, improvements in designing electrical circuits under process, voltage, and temperature variations are desirable.